1. Field of the Invention
The invention relates to the field of metal-oxide-semiconductor transistors. More particularly, it relates to the field of high speed submicron channel transistors. The invention realizes a transistor with a VLSI manufacturable process.
2. Description of Relevant Art
In submicron transistors hot electron injection into the gate is a serious reliability problem. Structures have been proposed in the attempt to design a high speed VLSI manufacturable submicron MOS transistor which exhibits resistance to hot electron degradation.
One such device is the lightly doped drain (LDD) transistor of FIG. 1. The LDD structure increases the transistor's resistance to hot electron degradation by decreasing the peak electric field of the device. The electric field is reduced by implanting lightly doped n- regions (between the gate edge and source/drain regions), thereby spreading the drain voltage drop over a wider depletion region than with traditional devices. This technique, however, shows a significant increase in the source/drain series resistance of the device due to the n+ to gate offset caused by the n- implant. Since the n- region is not located under the gate, interface states generated during hot electron injection can reduce drive current significantly by reducing mobility. In addition, hot electron injection into the spacer region can result in trapped charge causing a local increase in the threshold voltage leading to an increase in series resistance. This in turn lowers drive current.
Another structure proposed to decrease hot electron degradation in submicron metal-oxide-semiconductor transistors is the gate to drain overlap LDD structure (GOLD) of FIG. 2. With the GOLD structure a gate is formed above a lightly doped n- drain region creating a gate overlap of the drain. The GOLD structure, however, is not manufacturable in a production environment. The GOLD process depends on a natural oxide (5-10 .ANG.) for an etch stop and requires a selective oxide to minimize the n+ to gate offset. Both these steps are difficult to control in a manufacturing environment. In addition the polysilicon is undercut underneath the CVD (1) oxide which is not controllable and difficult to measure. The GOLD device uses a polysilicon gate overlap over the n- region to significantly reduce the lateral electric field thereby minimizing hot electron generation. In addition, the polysilicon gate overlap minimizes series resistance due either to the lower doping or interface states. The gate to drain overlap structure, however, increases the gate/drain capacitance of the transistor. Though the increased gate/drain capacitance reduces the transistors speed and gain, the ability to fabricate shorter channel devices compensates in both higher transistor speeds and gain.
The final structure proposed for a reliable submicron transistor is the LDD transistor with an inverse T-gate shown in FIG. 3. The ITLDD also features a gate overlap (over the n-region) which produces that same benefits as observed in the GOLD device. The inverse TLDD or (ITLDD) transistor also features a self aligned n- gate to drain overlap and a self aligned n+ source/drain implant. The self alignment process minimizes the n+ to gate offset. Like the GOLD structure, however, the ITLDD transistor has a higher gate to drain capacitance due to the gate to drain overlap. The high capacitance reduces the device's performance, however, the ability to make shorter channels compensates for this limitation. The ITLLD structure is inappropriate for VLSI circuits because the inverse T-gate process requires a timed etch. When etching the polysilicon layer to form the inverse T-gate there is no end point detection available to signal that the appropriate polysilicon overlap (shelf) thickness is present. Since the n- lightly doped drain region is implanted through the polysilicon shelf, any inconsistency in the shelf thickness would create an nonuniform doping structure.
Thus, what is desired is a high speed submicron transistor which is resistant to hot electron degradation and has a VLSI manufacturable process.